教員情報 - 小松　聡 | 東京電機大学

コマツ　サトシ KOMATSU Satoshi
小松　聡

所属東京電機大学工学部電子システム工学科

東京電機大学大学院先端科学技術研究科電気電子システム工学専攻

東京電機大学大学院工学研究科電気電子工学専攻

職種教授

著書・論文歴
1.	著書	はかる×わかる半導体入門編改訂版 (共著) 2020/12
2.	著書	電子回路 (共著) 2019/12
3.	著書	はかる×わかる半導体応用編 (共著) 2019/05
4.	著書	はかる×わかる半導体　半導体テスト技術者検定3級問題集 (共著) 2014/12
5.	著書	ウェスト&ハリス CMOS VLSI 回路設計応用編 (共著) 2014/01
6.	著書	はかる×わかる半導体入門編 (共著) 2013/05
7.	著書	Dependable Computing Systems (共著) 2005
8.	著書	Formal Methods and Models for System Design -- A System Level Perspective -- (共著) 2004
9.	論文	A Comparator with Controllable Offset Voltage Variation for Stochastic Flash ADC Proc. of The 25th Workshop on Synthesis And System Integration of Mixed Information Technologies (共著) 2024/03/11
10.	論文	A PVT Variation Dependencies of VCO in Frequency Locked Loop 2023 30th IEEE International Conference of Electronics, Circuits and Systems (ICECS) (共著) 2023/12/04
11.	論文	Automatic Generation System of Capacitive MEMS Accelerometers 2023 Symposium on Design, Test, Integration & Packaging of MEMS/MOEMS (DTIP) (共著) 2023/05/30
12.	論文	Capacitor Insertion Methodology to power Distribution Network for Improving Power Integrity DesignCon 2019 (共著) 2019/01
13.	論文	A Framework for Automatic Generation of Fully Synthesizable ADPLL Proc. of 25th IEEE International Conference on Electronics Circuits and Systems (共著) 2018/12
14.	論文	Efficient Test Generation Framework for Analog LSI with Behavior Model Proc. of International Conference on Advanced Technologies for Communications (ATC'18) (共著) 2018/10
15.	論文	A Low-Voltage Hysteresis Comparator for Low Power Applications 2017 24th IEEE International Conference on Electronics, Circuits and Systems (ICECS) (共著) 2017/12
16.	論文	Characteristics Optimization of Stochastic ADC and Its Automatic Generation System 2017 15th IEEE International New Circuits and Systems Conference (NEWCAS) (共著) 2017/06
17.	論文	Power Supply Voltage Control for Eliminating Overkills and Underkills in Delay Fault Testing IEICE Transactions on Electronics E99-C (10),1219-1225頁 (共著) 2016/10
18.	論文	A Comparative Study of Body Biased Time-to-Digital Converters Based on Stochastic Arbiters and Stochastic Comparators The 14th IEEE International NEWCAS Conference (共著) 2016/06
19.	論文	Dynamic Power Integrity Control of ATE for Eliminating Overkills and Underkills in Device Testing Journal of Electronic Testing 32 (3),257-271頁 (共著) 2016/04
20.	論文	A Novel Circuit for Transition-Edge Detection: Using a Stochastic Comparator Group to Test Transition-Edge Proc. of 2014 IEEE Asian Test Symposium (共著) 2014/11
21.	論文	Statistical Silicon Results of Dynamic Power Integrity Control of ATE for Eliminating Overkills and Underkills Proc. of 2014 IEEE International Test Conference (共著) 2014/09
22.	論文	A Structured Routing Architecture for Practical Application of Character Projection Method in Electron-Beam Direct Writing IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences Vol.E97-A (8),1688-1698頁 (共著) 2014/08
23.	論文	A Flash TDC with 2.6-4.2ps Resolution Using a Group of Unbalanced CMOS Arbiters IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences Vol. E97-A (No. 3),777-780頁 (共著) 2014/03
24.	論文	High-throughput Electron Beam Direct Writing of VIA Layers by Character Projection with One-dimensional VIA Characters IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences Vol. E96-A (12),2458-2466頁 (共著) 2013/12
25.	論文	A Novel Test Structure for Measuring Variance of Threshold Voltage in MOSFETs Proc. of 2013 IEEE International Test Conference (共著) 2013/09
26.	論文	A Stochastic Sampling Time-to-Digital Converter with Tunable 180-770fs Resolution, INL less than 0.6LSB, and Selectable Dynamic Range Offset Proc. of IEEE Custom Integrated Circuits Conference (CICC) (共著) 2013/09
27.	論文	A structured routing architecture and its design methodology suitable for high-throughput electron beam direct writing with character projection method Proc. of ACM International Symposium on Physical Design (ISPD 2013),,69-76頁 (共著) 2013/03
28.	論文	Practical proof of CP element based design for 14nm node and beyond Proc. of SPIE2013 Advanced Lithography (共著) 2013/03
29.	論文	High-throughput Electron Beam Direct Writing of VIA Layers by Character Projection using Character Sets Based on One-dimensional VIA Arrays with Area-efficient Stencil Design Proc. of 18th Asia and South Pacific Design Automation Conference (ASP-DAC 2013),255-260頁 (共著) 2013/01
30.	論文	A New Procedure for Measuring High-Accuracy Probability Density Functions Proc. of 2012 IEEE Asian Test Symposium (共著) 2012/11
31.	論文	Power Integrity Control of ATE for Emulating Power Supply Fluctuation on Customer Environment Proc. of IEEE International Test Conference 2012 (共著) 2012/11
32.	論文	A CMOS Flash TDC with 0.84-1.3ps Resolution Using Standard Cells Proc. of 2012 IEEE RFIC Symposium,527-530頁 (共著) 2012/06
33.	論文	CP element-based design for 14nm node EBDW high-volume manufacturing Proc. of 2012 SPIE Advanced Lithography (共著) 2012/02
34.	論文	Novel technique for minimizing the comparator delay dispersion in 65nm CMOS technology Proc. of 18th IEEE International Conference on Electronics, Circuits and Systems (ICECS),220-223頁 (共著) 2011/12
35.	論文	Application of a continuous-time level crossing quantization method for timing noise measurements Proc. of 2011 IEEE International Test Conference (ITC) (共著) 2011/09
36.	論文	An Equivalent-Time and Clocked Approach for Continuous-Time Quantization Proc. of IEEE International Symposium on Circuits and Systems 2011 (ISCAS 2011),2529-2532頁 (共著) 2011/05
37.	論文	Clocked Comparator for High-Speed Applications in 65nm Technology Proc. of IEEE Asian Solid-State Circuits Conference 2010 (A-SSCC2010),277-280頁 (共著) 2010/11
38.	論文	An Automatic Test Generation Framework for Digitally-Assisted Adaptive Equalizers in High-Speed Serial Links Proc. of Design Automation & Test in Europe 2010 (DATE 2010),1755-1760頁 (共著) 2010/03
39.	論文	Signature-Based Testing for Adaptive Digitally-Calibrated Pipelined Analog-to-Digital Converters Proc. of IEEE 8th International Conference on ASIC (ASICON2009) (共著) 2009/10
40.	論文	GA-Based Test Generation for Digitally-Assisted Adaptive Equalizers in High-Speed Serial Links Proc. of IEEE East-West Design & Test Symposium (EWDTS2009),287-292頁 (共著) 2009/09
41.	論文	Interconnect-Aware Pipeline Synthesis for Array-Based Architectures IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences Vol. E92-A (No. 6),1464-1475頁 (共著) 2009/06
42.	論文	Signature-Based Testing for Digitally-Assisted Adaptive Equalizers in High-Speed Serial Links Proc. of 14th IEEE European Test Symposium (ETS'09),107-112頁 (共著) 2009/05
43.	論文	Targeting Leakage Constraints during ATPG Proc. of 5th IEEE International Workshop on Silicon Debug and Diagnosis (SDD08),225-230頁 (共著) 2008/04
44.	論文	Using Counterexample Analysis to Minimize the Number of Predicates for Predicate Abstraction Proc. of 5th International Symposium on Automated Technology for Verification and Analysis,553-563頁 (共著) 2007/10
45.	論文	Formal Verification of Hardware/Software Co-designs with Translation into Representations in State Transitions Electronics and Communications in Japan, Part 2 Electronics 9 (7),11-19頁 (共著) 2007/07
46.	論文	UML-based Specification Method of Hardware IPs for Efficient IP Reuse Proc. of International UML-SoC Workshop at Design Automation Conference,23-30頁 (共著) 2007/06
47.	論文	VLSI CAD Education and Exercise Course with Public Domain Tools Proc. of IEEE International Conference on Microelectronic Systems Education (MSE07),111-112頁 (共著) 2007/06
48.	論文	Interconnect-aware Pipeline Synthesis for Array based Reconfigurable Architectures Proc. of International Embedded Systems Symposium 2007,121-134頁 (共著) 2007/05
49.	論文	Equivalence Checking in C-based System-Level Design by Sequentializing Concurrent Behaviors Proc. of IASTED International Conference on Advances in Computer Science and Technology,36-42頁 (共著) 2007/04
50.	論文	Protocol Transducer Synthesis using Divide and Couquer Approach Proc. of Asia and South Pacific Design Automation Conference,280-285頁 (共著) 2007/01
51.	論文	Dynamically Reconfigurable Protocol Transducer Proceedings of the International Conference on Field Programmable Technology (ICFPT06),341-344頁 (共著) 2006/12
52.	論文	Synchronization Verification in System-Level Design with ILP Solvers IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences Vol. E89-A (No. 12),3387-3396頁 (共著) 2006/12
53.	論文	The AMS Extension to System Level Design Language--SpecC IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences Vol. E89-A (No. 12),3397-3407頁 (共著) 2006/12
54.	論文	A New Trial on VLSI Test Exercise Course for Undergraduate/Graduate School in EE Department Proc. of 6th International Workshop on Microelectronics Education,92-95頁 (共著) 2006/06
55.	論文	Automatic Protocol Transducer Synthesis aiming at facilitating IP-Reuse Proc. of (International Workshop on Logic and Synthesis (IWLS2006),164-170頁 (共著) 2006/06
56.	論文	An Optimization of Bus Interconnects Pitch for Low-Power and Reliable Bus Encoding Scheme Proc. of 2006 IEEE International Symposium on Circuits and Systems,1723-1726頁 (共著) 2006/05
57.	論文	Low Power and Fault Tolerant Encoding Methods for On-Chip Data Transfer in Practical Applications IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences Vol. E88-A (No. 12),3282-3289頁 (共著) 2005/12
58.	論文	Pipeline scheduling for array based reconfigurable architectures considering interconnect delays Proc. of 4th IEEE International Conference on Field Programmable Technologies,137-144頁 (共著) 2005/12
59.	論文	AMS Extensions for Timed/Untimed System Level Design Language Proc. of FDL'05,77-80頁 (共著) 2005/09
60.	論文	Synchronization Verification in System-Level Design with ILP Solver Proc. of 3rd ACM-IEEE International Conference on Formal Methods and Models for Codesign (共著) 2005/07
61.	論文	System Level Design Language Extensions for Timed/Untimed Digital-Analog Combined System Design Proc. of GLSVLSI,130-133頁 (共著) 2005/03
62.	論文	Low Power and Fault Tolerant Encoding Methods for On-Chip Data Transfer Proc. of 12th Workshop on Synthesis And System Integration of Mixed Information Technologies,34-40頁 (共著) 2004/10
63.	論文	Practical Course of Design, Fabrication and Testing of CMOS Gate Array Proc. of 5th European Workshop on Microelectronics Education (共著) 2004/04
64.	論文	Irredundant Low Power Address Bus Encoding Techniques Based on Adaptive Codebooks IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences Vol. E86-A (No. 12),3001-3008頁 (共著) 2003/12
65.	論文	Verification of Synchronization in SpecC Description with the Use of Difference Decision Diagrams IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences Vol. E86-A (No. 12),3192-3199頁 (共著) 2003/12
66.	論文	Comparative study on Verilog-based and C-based hardware design education Proc. of International Conference on Microelectronic Systems Education (共著) 2003/06
67.	論文	Engineering Changes in Field Modifiable Architectures Proc. of International Conference on Formal Methods and Models for Co-Desgn,87-94頁 (共著) 2003/06
68.	論文	An Ultra Low Power Motion Estimation Processor for MPEG2 HDTV Resolution Video IEICE Trans. on Electronics Vol. E86-C (No. 4),561-569頁 (共著) 2003/04
69.	論文	Field Modifiable Architecture with FPGAs and its Design/Verification/Debugging Methodologies Proc. of Annual Hawaii International Conference on System Sciences,279 (共著) 2003/01
70.	論文	Irredundant Address Bus Encoding Techniques based on Adaptive Codebooks for Low Power Proc. Asia South Pacific Design Automation Conference,9-14頁 (共著) 2003/01
71.	論文	Field Modifiable Architecture with FPGAs and its Design Methodology Proc. of IEEE International Conference on Field-Programmable Technology,382-385頁 (共著) 2002/12
72.	論文	Field Modifiable Architecture and its Design Method Proc. of ACM SIGPLAN Conference on Programming Language Design and Implementation (共著) 2002/06
73.	論文	Field Modifiable Architecture and Its Design Methodology -System Design Without Logic Synthesis- Proc. of IEEE/ACM International Workshop on Logic and Synthesis,103-108頁 (共著) 2002/06
74.	論文	An Inter-University Joint Program for a Trial of IP-Based System LSI Design Proc. of 4th European Workshop on Microelectronics Education (共著) 2002/05
75.	論文	An Ultra Low Power, Realtime MPEG2 MP@HL Motion Estimation Processor Core with SIMD Datapath Architecture Optimized for Gradient Descent Search Algorithm Proc. of IEEE 2002 Custom Integrated Circuits Conference,167-170頁 (共著) 2002/05
76.	論文	Bus Data Encoding with Coupling-driven Adaptive Code-book Method for Low Power Data Transmission Proc. of European Solid-State Circuits Conference,312-315頁 (共著) 2001/09
77.	論文	Bus Data Encoding with Adaptive Code-book Method for Low Power IP Based Design Proc. of International Workshop on IP-Based Synthesis and SoC Design,77-81頁 (共著) 2000/12
78.	論文	Approaches for Reducing Power Consumption in VLSI Bus Circuits IEICE Trans. on Electronics Vol. E83-C (No. 2),153-160頁 (共著) 2000/02
79.	論文	Adaptive Codebook Encoding for Low-Power Chip Interface Electronics and Communications in Japan, Part 2: Electronics Vol. 83 (No. 1),17-24頁 (共著) 2000/01
80.	論文	Associative Memory with Minimum Hamming Distance Detector and its Application to Bus Data Proc. of AP-AS 99 (共著) 1999/08
81.	論文	マイクロプロセッサにおけるデータバス信号系列の統計的解析および疑似データ生成モデルの提案電子情報通信学会論文誌 Vol. J82-A (No. 8),1406-1408頁 (共著) 1999/08
82.	論文	適応型コード帳符号化による低消費電力チップインタフェースの検討電子情報通信学会論文誌 Vol. J82-C-II (No. 4),203-209頁 (共著) 1999/04
83.	論文	Low Power Chip Interface Based on Bus Data Encoding with Adaptive Code-Book Method Proc. of 9th Great Lakes Symposium on VLSI,368-371頁 (共著) 1999/03
84.	論文	Low Power Microprocessors for Comparative Study on Bus Architecture and Multiplexer Architecture Proc. of Asia and South Pacific Design Automation Conference,323-324頁 (共著) 1998/02